1. Field of the Invention
The present invention relates to semiconductor integrated circuits for converting serial data into parallel data and storing the data, and more particularly to semiconductor integrated circuits such as LCD drivers for driving liquid crystal displays (LCDs) with random access memories (RAMs) embedded therein.
2. Related Art
Some LCD drivers for driving a number of areas separated in the segment direction of LCD convert serial data, which is input via an interface, into parallel data and write it into embedded RAMs and then read out the data stored in the RAMs so as to produce driving signals. FIG. 4 illustrates such a conventional LCD driver.
As shown in FIG. 4, an LCD driver 100 includes a shift register 109 for converting serial data (DATA), which is input together with a clock signal CLK, into parallel data, a latch circuit 110 for latching the parallel data, and a RAM 111 for storing the latched data.
Moreover, the LCD driver 100 includes a counter 101 for counting clock signals CLK and outputting a pulse every 9 counts from an output terminal Q9; a flip-flop FF1 for outputting a pulse signal S2 in synchronization with a pulse signal S1 output from the counter 101; a delay circuit 102 for outputting a pulse signal S3 obtained by delaying the pulse signal S2; a flip-flop FF2 for outputting a pulse signal S4 in synchronization with the pulse signal 3; a delay circuit 103 for outputting a pulse signal S5 obtained by delaying the pulse signal S4; a buffer circuit 104; two NOR circuits 105 and 106; two inverters 107 and 108; and a command producing circuit 112 for controlling data writing/reading to and from the RAM111.
FIG. 5 shows operations at parts of the LCD driver shown in FIG. 4. After an inversion resetting signal (RESET bar) turns to a high-level in response to canceling the reset state, a 1-bit data/command identifier D/C and 8-bit data D7 to D0 are sequentially input to the shift register 109 in synchronization with the clock signal CLK as shown in FIG. 5, so that the total 9-bit signals are stored in a flip-flop in the shift register 109. In the meantime, the counter 101 counts 9 pulses included in the clock signal CLK and outputs the pulse signal S1 from the output terminal Q9.
The flip-flop FF1 turns the pulse signal S2 to a high-level in synchronization with the leading edge of the pulse signal S1. The delay circuit 102 delays the pulse signal S2 by a predetermined period of time and outputs the pulse signal S3. The pulse signal S3 is inverted by the NOR circuit 105. Here, the inverted pulse signal S3 is input to a reset terminal R of the flip-flop FF1, so that the flip-flop FF1 is reset and the pulse signal S2 returns to a low-level. As a result, the flip-flop FF1 outputs the pulse signal S2 including a pulse having a pulse width the same as the time delayed by the delay circuit 102. The pulse width of the pulse signal S3 is also the same as that of the pulse signal S2.
The latch circuit 110 latches the 1-bit data/command identifier D/C and the 8-bit data D7 to D0, which are output as parallel data from the shift register 109, in synchronization with the trailing edge of the pulse signal S3. Since the pulse signal S3 is produced by delaying the pulse signal S2 with the delay circuit 102, the signals are latched by the latch circuit after completely outputting the signals from the shift register 109.
The flip-flop FF2 turns the pulse signal S4 to a high-level in synchronization with the leading edge of the pulse signal S3. The delay circuit 103 delays the pulse signal S4 by a predetermined period of time and outputs the pulse signal S5. The pulse signal S5 is inverted by the NOR circuit 106. Here, the inverted pulse signal S5 is input to a reset terminal R of the flip-flop FF2, so that the flip-flop FF2 is reset and the pulse signal S4 returns to a low-level. As a result, the flip-flop FF2 outputs the pulse signal S4 including a pulse having a pulse width the same as the time delayed by the delay circuit 103. The pulse width of the pulse signal S5 is the same as that of the pulse signal S4.
The pulse signal S5 from the buffer circuit 104 as well as the data D7 to D0 from the latch circuit 110 are input to the RAM111. Moreover, the pulse signal S5 from the buffer circuit 104 as well as the data/command identifier D/C and the data D7 to D0 from the latch circuit 110 are input to the command producing circuit 112. When the data/command identifier D/C indicates a command, the command producing circuit 112 determines the timing for data writing/reading to and from the RAM111 and designates an address in accordance with the command sent as the data D7 to D0 and with the pulse signal S5. On the other hand, when the data/command identifier D/C indicates data, the RAM111 writes the data D7 to D0 into designated addresses. Here, the pulse width of the pulse signal S5, which indicates a period of time for writing data into the RAM111, is determined by the time delayed by the delay circuit 103.
As described above, in the conventional semiconductor integrated circuit, the period of time for writing data into a RAM is determined by time delayed by a delay circuit. As a result, the delay circuit needs to be adjusted in some cases when the RAM is replaced with new one, and also shortening the cycle of data writing/reading remains difficult.
In light of the above problems, the present invention aims to provide a semiconductor integrated circuit that includes a function of converting serial data into parallel data in order to store the data and also enjoys stable operation even when the cycle of the data writing/reading is shortened.